Design of Synaptic Driving Circuit for TFT eFlash-Based Processing-In-Memory Hardware Using Hybrid Bonding

This paper presents a synaptic driving circuit design for processing in-memory (PIM) hardware with thin-film transistor (TFT) embedded flash (eFlash) binary/ternary-weight neural network (NN). An eFlash-based cell capable of programming negative weight values to store binary/ternary (i.e., ±1, 0) and circuits erase, program, read operations arrays have been proposed. The proposed improve the calculation accuracy PIM operation by precisely sensing current eFlash target (50 nA ± 0.5 nA) using pulse train. In addition, during operation, pulse-width modulation (PWM) conversion converts 8-bit input data into one continuous PWM minimize non-linearity in integration step neuron circuit. prototype chip, including circuit, digital blocks, is designed laid out as accelerator weighted NN size 324 × 80 10 0.35 μm CMOS process. Hybrid bonding technology bump wire used package die TFT synapse array dies single chip package.